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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11407-3E
MEMORY
CMOS
2 x 512 K x 16 BIT / 2 x 256 K x 32 BIT SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES171625/173225-12/-15
s DESCRIPTION
The Fujitsu MB81ES171625/173225 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 bit memory cells accessible in a 2x512Kx16 bit / 2x256Kx32 bit format. The MB81ES171625/173225 features a fully synchronous operation referenced to a positive edge clock same as that of SDRAM operation, whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81ES171625/173225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM). The MB81ES171625/173225 is dedicated for SiP (System in a Package), and ideally suited for various embedded/ consumer applications including digital AVs, and image processing where a large band width and low power consumption memory is needed. * : FCRAM is a trademark of Fujitsu Limited, Japan.
s PRODUCT LINEUP
Parameter Clock Frequency (Max) Burst Mode Cycle Time (Min) Access Time From Clock (Max) XRAS Cycle Time (Min) Operating Current (Max) (IDD1) Power Down Mode Current (Max) (IDD2P) Self-refresh Current (Max) (IDD6) CL = 1 CL = 2 CL = 1 CL = 2 MB81ES171625/173225 -12 85 MHz 23.4 ns 11.7 ns 21.9 ns 10.2 ns 75 ns 30 mA 1 mA 5 mA -15 66.7 MHz 30 ns 15 ns 27 ns 12 ns 75 ns 30 mA 1 mA 5 mA
MB81ES171625/173225-12/-15
s FEATURES
* * * * * FCRAM core with Single Data Rate SDRAM interface 512 K word x 16 bit x 2 bank or 256 K word x 32 bit x 2 bank organization Single +1.8 V Supply 0.15 V tolerance CMOS I/O interface Programmable burst type, burst length, and CAS latency Burst type : Sequential Mode, Interleave Mode Burst length : 1, 2, 4, 8, full column (64 : x16 bit, 32 : x32 bit) CAS latency MB81ES171625/173225-12 CL = 1 (Min tCK = 23.4 ns, Max 42.7 MHz) CL = 2 (Min tCK = 11.7 ns, Max 85 MHz) 2 K refresh cycles every 16 ms Auto- and Self-refresh CKE power down mode Output Enable and Input Data Mask Burst Stop command at full column burst Burst read/write 85 MHz/66.7 MHz Clock frequency
* * * * * * *
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MB81ES171625/173225-12/-15
s PAD LAYOUT
MB81ES171625
DSE BME TBST DQC VSS VDD VSS VDD DQ8 DQ9 DQ10 DQ11 VDDQ VSSQ DQ12 DQ13 DQ14 DQ15 DQM1 A12 A11 BA A10 (AP) A9 A8 A7 A6 CLK CKE VSSQ S16 VDDQ XCS XRAS XCAS XWE A5 A4 A3 A2 A1 A0 DQM0 DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0 VDD VSS VDD VSS
PAD No.84
PAD
PAD No.1
(Continued)
3
MB81ES171625/173225-12/-15
(Continued)
MB81ES173225
DSE BME TBST DQC DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 VSS VDD VSS VDD DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 DQM2 DQM3 A12 A11 BA A10(AP) A9 A8 A7 A6 CLK CKE VSSQ S32 VDDQ XCS XRAS XCAS XWE A5 A4 A3 A2 A1 A0 DQM1 DQM0 DQ15 DQ14 DQ13 DQ12 VSSQ VDDQ DQ11 DQ10 DQ9 DQ8 VDD VSS VDD VSS DQ7 DQ6 DQ5 DQ4 VSSQ VDDQ DQ3 DQ2 DQ1 DQ0
PAD No.84
PAD
PAD No.1
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MB81ES171625/173225-12/-15
s PAD DESCRIPTIONS
* MB81ES171625 Symbol VDD, VDDQ VSS, VSSQ DQ15 to DQ0 DQM1 to DQM0 XWE XCAS XRAS XCS BA AP A12A0 CKE CLK TBST BME DSE DQC S16 * MB81ES173225 Symbol VDD, VDDQ VSS, VSSQ DQ31 to DQ0 DQM3 to DQM0 XWE XCAS XRAS XCS BA AP A12 to A0 CKE CLK TBST BME DSE DQC S32 Supply Voltage Ground Data I/O DQ MASK Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select Auto Precharge Enable Address Input Clock Enable Clock Input BIST Control Burn In Enable Disable BIST Output x 32 Select 5 * Row : A12 to A0 * Column : A4 to A0 Supply Voltage Ground Data I/O DQ MASK Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select Auto Precharge Enable Address Input Clock Enable Clock Input BIST Control Burn In Enable Disable BIST Output x 16 Select Function * Row : A12 to A0 * Column : A5 to A0 Function
MB81ES171625/173225-12/-15
s BLOCK DIAGRAM
MB81ES171625
CLK CKE S16
To each block CLOCK BUFFER BANK-1
XRAS
BANK-0
DSE BME XCS XRAS XCAS XWE
CONTROL SIGNAL LATCH COMMAND DECODER
XCAS
XWE
MODE REGISTER
FCRAM CORE (8,192 x 64 x 16)
A12 to A0, A10/AP BA
ADDRESS BUFFER/ REGISTER & BANK SELECT COLUMN ADDRESS COUNTER
ROW ADDR.
13
COL. ADDR.
6 I/O
DQM1 to DQM0
DQ15 to DQ0
I/O DATA BUFFER/ REGISTER
16 VCC VCCQ VSS/VSSQ
TBST DQC
BIST
(Continued)
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MB81ES171625/173225-12/-15
(Continued)
MB81ES173225
CLK CKE S32
To each block
CLOCK BUFFER
BANK-1 BANK-0
XRAS DSE BME XCS XRAS XCAS XWE
CONTROL SIGNAL LATCH COMMAND DECODER
XCAS
XWE
MODE REGISTER
FCRAM CORE (8,192 x 32 x 32)
A12 to A0, A10/AP BA
ADDRESS BUFFER/ REGISTER & BANK SELECT
ROW ADDR.
13
COLUMN ADDRESS COUNTER
COL. ADDR.
5 I/O
DQM3 to DQM0
I/O DATA BUFFER/ REGISTER
DQ31 to DQ0 32 VCC VCCQ VSS/VSSQ TBST DQC
BIST
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MB81ES171625/173225-12/-15
s FUNCTIONAL TRUTH TABLE
1. Command Truth Table
Function Device Deselect* No Operation*1 Burst Stop*2 Read*3 X16 X32
1
Command DESL NOP BST READ
CKE n-1 H H H H H H H H H H H H H H H n X X X X X X X X X X X X X X X
XCS XRAS XCAS H L L L L L L L L L L L L L L X H H H H H H H H H H L L L L X H H L L L L L L L L H H H L
XWE X H L H H H H L L L L H L L L
BA X X X V V V V V V V V V V X L
A 10 A 12 to (AP) A6 X X X L L H H L L H H V L H L X X X X X X X X X X X V X X V
A5 X X X V X V X V X V X V X X V
A4 to A0 X X X V V V V V V V V V X X V
Read with Auto-pre- X16 READA charge*3 X32 Write*3 X16 X32 WRIT WRITA ACTV
5
Write with Auto-pre- X16 charge*3 X32 Bank Active*
4
Precharge Single Bank* Precharge All Banks*5 Mode Register Set*5, *6
PRE PALL MRS
V = Valid, L = Logic Low, H = Logic High, X = either L or H. n = State at current clock cycle, n-1 = state at 1 clock cycle before n. *1: NOP and DESL commands have the same effect on the part. At DESL command (XCS = "H") , all input signal are ignored, but hold the internal state. NOP command (XCS = "L", XRAS = XCAS = XWE = "H") is no effect on device operation and the internal state continue. *2: BST command is effective on every Burst Length. (BL = 1, 2, 4, 8, full column) *3: READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been activated (ACTV command) . Refer to "s STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)." *4 ACTV command should be issued only after the corresponding bank has been precharged (PRE or PALL command) . *5: Required after power up. Refer to "17. Power-Up Initialization" in "s FUNCTIONAL DESCRIPTION." *6: MRS command should be issued only after all banks have been precharged (PRE or PALL command) and DQ is in High-Z. Refer to "s STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)." Notes: * All commands assumes no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock. * TBST,BME and DSE should be held Low. * S16 should be held VIH, and S32 should be held VIL.
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MB81ES171625/173225-12/-15
2. DQM Truth Table
Function Data Write/Output Enable Data Mask/Output Disable Command ENBL MASK CKE n-1 H H n X X DQM L H
V = Valid, L = Logic Low, H = Logic High, X = either L or H. n = State at current clock cycle, n-1 = state at 1 clock cycle before n. Notes: * MB81ES171625; DQM0 and DQM1 controls DQ7 to DQ0 and DQ15 to DQ8, respectively. * MB81ES173225; DQM0, DQM1, DQM2 and DQM3 controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and DQ31 to DQ24, respectively. * TBST, BME and DSE should be held Low. * S16 should be held VIH, and S32 should be held VIL. * All commands assumes no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock.
3. CKE Truth Table
Current State Bank Active Function Command REF SELF SELFX PD CKE n-1 H L L H H L L H H L L n L L H H L H H L L H H XCS XRAS XCAS XWE BA X X X L L L H L H L H X X X L L H X H X H X X X X L L H X H X H X X X X H H H X H X H X X X X X X X X X X X X
A10 (AP)
A12 to A0 X X X X X X X X X X X
Clock Suspend Mode Entry *1 CSUS
1
X X X X X X X X X X X
Any (Except Idle) Clock Suspend Continue *
Clock Suspend Clock Suspend Mode Exit Idle Idle Self Refresh Idle Power Down Auto-refresh Command * Self-refresh Entry * * Self-refresh Exit *4 Power Down Entry *3 Power Down Exit
2, 3 2
V = Valid, L = Logic Low, H = Logic High, X = either L or H. n = State at current clock cycle, n-1 = state at 1 clock cycle before n. *1: CSUS command requires that at least one bank is active. Refer to "s STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)." *2: REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL command) . Refer to "s STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)." *3: SELF and PD commands should be issued only after the last read data have been appeared on DQ. *4: CKE should be held High during tREFC. Notes: * TBST,BME and DSE should be held Low. * S16 should be held VIH, and S32 should be held VIL. * All commands assumes no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock.
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MB81ES171625/173225-12/-15
4. Operation Command Table (Applicable to single bank)
Current State XCS XRAS XCAS XWE H L L L L Idle L L L L L H L L L Bank Active L L L L L L H L L L L Read L L L L L X H H H H L L L L L X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L X H H L L H H H L L X H L H L H L L H L X H L H L H L L H L X H L H L H L L H L Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS Begin Read; Determine AP Begin Write; Determine AP Illegal*2 Precharge Precharge*1 Illegal NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, NewRead; Determine AP Terminate Burst, Start Write; Determine AP*4 Illegal*2 Terminate Burst, Precharge Idle Terminate Burst, Precharge Idle*1 Illegal NOP NOP NOP*1 Illegal*2 Bank Active after tRCD NOP NOP*1 Auto-refresh or Self-reresh*3, *5 Mode Register Set (Idle after tRSC) *3, *6 Function
(Continued)
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MB81ES171625/173225-12/-15
Current State
XCS XRAS XCAS H L L L X H H H H L L L L L X H H H H L L L L L X H H H H L L L L L X H H L L H H H L L X H H L L H H H L L X H H L L H H H L L
XWE X H L H L H L L H L X H L H L H L L H L X H L H L H L L H L
Addr X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP AP X MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE PALL REF/SELF MRS Illegal Illegal*2 Illegal Illegal*2
Function NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine AP*4 Terminate Burst, New Write; Determine AP Illegal*2 Terminate Burst, Precharge Idle Terminate Burst, Precharge Idle*1 Illegal NOP (Continue Burst to End Precharge Idle) Illegal
Write
L L L L L L H L L L
Read with Autoprecharge
L L L L L L H L L L
NOP (Continue Burst to End Precharge Idle) Illegal
Write with Autoprecharge
L L L L L L
(Continued)
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MB81ES171625/173225-12/-15
Current State
XCS XRAS XCAS H L L L L L L L L L H L L L L L L L L L H L L X H H H H L L L L L X H H H H L L L L L X H H H L L X H H L L H H H L L X H H L L H H H L L X H H L H L
XWE X H L H L H L L H L X H L H L H L L H L X H L X X X
Addr X X X BA, CA, AP BA, RA BA, AP AP X MODE X X X BA, CA, AP BA, RA BA, AP AP X MODE X X X X X X
Command DESL NOP BST WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST WRIT/WRITA ACTV PRE PALL REF/SELF MRS DESL NOP BST READ/READA/ WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS Illegal Illegal NOP*7 NOP*1 Illegal Illegal*2
Function
NOP (Idle after tRP)
BA, CA, AP READ/READA
Precharging
NOP (Bank Active after tRCD) NOP (Bank Active after tRCD) *1
BA, CA, AP READ/READA Illegal*2
Bank Activating
NOP (Idle after tREFC)
Refreshing
L L L
(Continued)
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MB81ES171625/173225-12/-15
(Continued) Current State
XCS H L L L
XRAS XCAS X H H H X H H L
XWE X H L X
Addr X X X X
Command DESL NOP BST READ/READA/ WRIT/WRITA ACTV/PRE/ PALL/REF/SELF/ MRS
Function NOP (Idle after tRSC)
Mode Register Setting
Illegal
L
L
X
X
X
ABBREVIATIONS : V = Valid, L = Logic Low, H = Logic High, X = either L or H. n = State at current clock cycle, n-1 = state at 1 clock before n. RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge *1: Entry may affect other bank. *2: Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of that bank. *3: Illegal if any bank is not idle. *4: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)" and "12. WRITE to READ Timing (Example @ CL = 1, BL = 4)" in "s TIMING DIAGRAMS." *5: SELF command should be issued only after the last read data has been appeared on DQ. *6: MRS command should be issued only when all DQ are in High-Z. *7: NOP in precharging or idle state. PRE may affect to the bank specified by BA and AP . Notes: * TBST,BME and DSE should be held Low. * S16 should be held VIH, and S32 should be held VIL. * All entries in OPERATION COMMAND TABLE assume that the CKE was High during the proceeding clock cycle and the current clock cycle. * Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence will be asserted after power shut down. * All commands assume no CSUS command on previous rising edge of clock. * All commands are assumed to be valid state transitions. * All inputs are latched on the rising edge of the clock.
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MB81ES171625/173225-12/-15
5. Command Truth Table for CKE
Current State CKE (n-1) H L L Selfrefresh L L L L L H Selfrefresh Recovery H H H H H H L L Power Down L L L L H H H H H All Banks Idle H H H H H H H L CKE (n) X H H H H H L X H H H H H L X H H L H H H H H H H H L L L L L L L X XCS XRAS XCAS X H L L L L X X H L L L L X X H L X L L L H L L L L H L L L L L L X X X H H H L X X X H H H L X X X H X L H H X H L L L X H H H L L L X X X H H L X X X X H H L X X X X H X X L H X X H L L X H H L H L L X XWE X X H L X X X X X H L X X X X X H X X X L X X X H L X H L X X H L X Addr X X X X X X X X X X X X X X X X X X X X X V V V X V X X X X X X X X Self-refresh*2 Illegal Invalid Illegal Auto-refresh Refer to "Operation Command Table". Power Down Refer to "Operation Command Table". Illegal Illegal*1 Invalid Exit Power Down Mode Idle NOP (Maintain Power Down Mode) Illegal Maintain Self-refresh Invalid Idle after tREFC Illegal Invalid Exit Self-refresh (Self-refresh Recovery Idle after tREFC) Function
(Continued)
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MB81ES171625/173225-12/-15
(Continued) Current State
CKE CKE (n-1) (n) H H
XCS XRAS XCAS XWE
Addr
Function
X
X
X
X
X
Refer to "Operation Command Table".
Bank Active Bank Activating Read/Write
H
L
X
X
X
X
X
Begin Clock Suspend next cycle
L H Clock Suspend Any State Other Than Listed Above L L L H H
X X H L X H L
X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
Invalid
Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer to "Operation Command Table". Illegal
V = Valid, L = Logic Low, H = Logic High, X = either L or H. n = State at current clock cycle, n-1 = state at 1 clock cycle before n. *1: CKE should be held High for tREFC period. *2: SELF command should be issued only after the last data has been appeared on DQ. Notes: * TBST,BME and DSE should be held Low. * S16 should be held VIH, and S32 should be held VIL. * All entries in "5. Command Truth Table for CKE" are specified at CKE (n) state and CKE input from CKE (n-1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE.
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MB81ES171625/173225-12/-15
s FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM Basic Function
Three major differences between SDR I/F FCRAMs and conventional DRAMs are : a synchronized operation, a burst mode, and a mode register. The synchronized operation is the fundamental difference. SDR I/F FCRAM uses a clock input for synchronization, while DRAM is basically asynchronous memory although it has been using two clocks, XRAS and XCAS. Each operation of DRAM is determined by their timing phase differences while each operation of the SDR I/F FCRAM is determined by commands and all operations are referenced to a rising edge of a clock. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to configure SDR I/F FCRAM operation and function into desired system conditions. "s MODE REGISTER TABLE" shows how the SDR I/F FCRAM can be configured for system requirements by mode register programming. The program to the mode resister should be excuted after all banks are precharged.
2. FCRAMTM
MB81ES171625/173225 utilizes FCRAM core technology. The FCRAM is an acronym for Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. Clock (CLK) Input and Clock Enable (CKE)
All input and output signals of the SDR I/F FCRAM use register type buffers. CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a rising edge of CLK. All outputs are validated by a rising edge of CLK. CKE is a high active clock enable signal. CKE controls the internal clock generator. CKE is latched by a rising edge of clock. CKE should become High level on the previous clock cycle when a basic command is issued. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the Power Down mode (standby) is entered with CKE = Low and this will make extremely low standby current.
4. Chip Select (XCS)
XCS enables all command inputs, XRAS, XCAS, XWE and address inputs. When XCS is High, command signals are negated but internal operations such as a burst cycle will not be suspended. If such a control isn't needed, XCS can be tied to ground level.
5. Command Input (XRAS, XCAS and XWE)
Unlike a conventional DRAM, XRAS, XCAS, and XWE do not directly imply SDR I/F FCRAM operations, such as Row address strobe by XRAS. Instead, each combination of XRAS, XCAS, and XWE input in conjunction with XCS input at the rising edge of the CLK determines SDR I/F FCRAM operations. Refer to "s FUNCTIONAL TRUTH TABLE."
6. Address Input (A12 to A0)
Address input selects an arbitrary location of each memory cell matrix, 524,288 (x16 bit) or 262,144 (x32 bit) . A total of 19( x 16 bit) or 18 ( x 32 bit) address input signals are required to decode 13 bit Row addresses and 6 bit (x16 bit) or 5 bit (x32 bit) Column addresses matrix. The SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , 13 bit Row addresses are initially latched and the remainder of 6 bit ( x 16 bit) or 5 bit ( x 32 bit) Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or a Write command (WRIT or WRITA) . A10 selects READ or READA, WRIT or WRITA and PRE or PALL.
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MB81ES171625/173225-12/-15
7. Bank Select (BA)
This SDR I/F FCRAM has two banks. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRITA) , and precharge commands (PRE or PALL) .
8. Data Inputs and Ooutputs (DQ15 to DQ0/DQ31 to DQ0)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input : tRAC; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.) tCAC; from the read command when tRCD is greater than tRCD (Min) at CL = 1. tAC ; from the rising edge of the clock after tRAC and tCAC. The polarity of the output data is identical to that of input data. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH) . Refer to "s AC CHARACTERISTICS".
9. Data I/O Mask (DQM1, DQM0/DQM3 to DQM0)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM = High is latched by a clock, input is masked at the same clock and output will be masked at the CL later while internal burst counter will increment by one or will go to the next stage depending on the burst type.
10. Burst Mode Operation
The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row address and by automatically generating column address. Access time and cycle time of Burst mode is specified as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and the burst count length of 1, 2, 4, 8 bits of boundary or full column. In order to terminate or move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required : (1) Burst Type The burst type can be selected either sequential or interleave mode. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. (2) Burst Mode Termination and Method of Next Stage Set Current Stage Next Stage Method (Assert the following command) Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Burst Read Burst Write Burst Write Burst Read Precharge Precharge 1st Step 2nd Step Read Command Mask Command (Normally 3 clock cycles) Write Command after Write Command Read Command Precharge Command Precharge Command
OWD
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MB81ES171625/173225-12/-15
(3) Counter Operation of Sequential Mode and Interleave Mode Starting Column Sequential Mode Burst Address Length A1 A0 A2 2 X X X 4 X X X 0 0 0 8 0 1 1 1 1 X X 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave Mode
0-1 1-0 0-1-2- 3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
11. Full Column Burst and Burst Stop Command (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation. BST command is applicable to terminate the burst operation. If BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When a read mode is interrupted by BST command, the output will be in High-Z. For the detailed rule, please refer to "8. READ Interrupted by Burst Stop (Example @ BL = Full Column) " in "s TIMING DIAGRAMS." When a write mode is interrupted by BST command, the data to be applied at the same time with BST command will be ignored.
12. Precharge and Precharge Option (PRE, PALL)
The SDR I/F FCRAM memory core is the same as a conventional DRAM's, requiring precharge and refresh operations. Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby state after precharge time (tRP) . The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by BA is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "s FUNCTIONAL TRUTH TABLE." 18
MB81ES171625/173225-12/-15
13. Auto-Refresh (REF)
The Auto-refresh uses the internal refresh address counter. SDR I/F FCRAM Auto-refresh command (REF) generates the Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be asserted every 7.8 s or a total 2048 refresh commands within a 16 ms period.
14. Self-Refresh Entry (SELF)
The Self-refresh function provides automatic refresh by an internal timer as well as the Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should be issued only after the last read data has been appeared on DQ. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms prior to the self-refresh mode entry.
15. Self-Refresh Exit (SELFX)
To exit the Self-refresh mode, apply minimum tSI after CKE brought high, and then the No operation command (NOP) or the Deselect command (DESL) should be asserted within one tREFC period. CKE should be held High within one tREFC period after tSI. Refer to "16. Self-Refresh Entry and Exit Timing" in "s TIMING DIAGRAMS" for the detail. It is recommended to assert an Auto-refresh command just after tREFC period to avoid the violation of refresh period. Note : When the burst refresh method is used, a total of 2048 auto-refresh commands must be asserted within 1 ms after the Self-refresh exit.
16. Mode Register Set (MRS)
The mode register of the SDR I/F FCRAM provides a variety of operations. The register consists of 3 operation fields; Burst Length, Burst Type, and CAS latency. Refer to "s MODE REGISTER TABLE." The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the address line. Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command (or part loses power) . MRS command should be issued only when DQ is in High-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of the SDR I/F FCRAM. Refer to "17. Power-Up Initialization".
17. Power-Up Initialization
SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. 2. 3. 4. 5. Apply the power and start the clock. Attempt to maintain either the NOP or DESL command at the input. Maintain stable power, stable clock, and NOP condition for a minimum of 500 s. Precharge all banks by the Precharge (PRE) or Precharge All command (PALL) . Assert minimum of 2 Auto-refresh commands (REF) . Program the mode register by the Mode Register Set command (MRS) .
In addition, it is recommended that DQM and CKE track VDD to insure that output is High-Z state. The Mode Register Set command (MRS) can be set before 2 Auto-refresh commands (REF) . It is possible to execute 5 before 4.
19
MB81ES171625/173225-12/-15
s STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)
MODE REGISTER SET
MRS
SELF
IDLE
SELFX
SELF REFRESH
REF CKE ACTV CKE\ (PD)
AUTO REFRESH
POWER DOWN
BANK ACTIVE SUSPEND
CKE\ (CSUS) CKE BST
BANK ACTIVE
BST
WRIT
WRIT WRITA READA READ
READ
READ
CKE
WRITE SUSPEND
CKE
WRITE
WRIT CKE\ (CSUS) WRITA CKE READA WRITA
READ
CKE\ (CSUS) READA
READ SUSPEND
PRE or PALL
WRITE SUSPEND
WRITE WITH AUTO PRECHARGE
READ WITH AUTO PRECHARGE
PRE or PALL
CKE
READ SUSPEND
CKE\ (CSUS)
PRE or PALL
CKE\ (CSUS)
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED
DEFINITION OF ALLOWS
Manual Input Automatic Sequence
Note : CKE\ means CKE goes Low-level from High-level.
20
MB81ES171625/173225-12/-15
s BANK OPERATION COMMAND TABLE
* Minimun Clock Latency or Delay Time for Single Bank Operation
Second command (same bank) First command
MRS
ACTV
READ READA
WRIT
WRITA
PRE
PALL
REF
SELF
BST
MRS
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
*4
tRCD
*4
tRAS
*3
tRAS
*3
1
READ
*1, *2 *1
1
1
1
1
1
*3
1
*3 *1 *1
1
*1
READA
BL + tRP
BL + tRP tWR tWR 1 1
BL + tRP
*3
BL + tRP
*3
BL + tRP
BL + tRP
BL + tRP 1
WRIT
*1, *2 *1
tDPL
*3
tDPL
*3 *1 *1
*1
WRITA
BL-1 + tDAL
*1, *2
BL-1 + tDAL tRP
BL-1 + tDAL 1
BL-1 + tDAL
*3
BL-1 + tDAL
*1
BL-1 + tDAL
*1, *5
BL-1 + tDAL 1
PRE
tRP
*2
1
tRP
tRP
*5
PALL
tRP
tRP
1
1
tRP
tRP
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
*1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: Assume tRAS (Min) is satisfied. *4: Assume no I/O conflict. *5: Assume the last data have been appeared on DQ. Illegal Command.
21
MB81ES171625/173225-12/-15
* Minimum Clock Latency or Delay Time for Multi Bank Operation
Second command (other bank) First command
*4 MRS ACTV
*4
*4
*4 WRITA PRE PALL REF SELF BST
READ READA WRIT
MRS
tRSC
tRSC
*1 *6 *6 *6 *6
tRSC
*5, *6
tRSC
*6
tRSC
tRSC
tRSC
ACTV
tRRD
*1, *3
1 1
*5
1 1
*5
1
*8
1
*8
1
*5
tRAS
*5
1
READ
*1, *2
1 BL + tRP
*1, *3
1
*5, *8
1
*5, *8
1
*5
1
*5 *1 *1
1
*1
READA
1
*1, *3
1 1
*5
1 1
*5
1 1
*5
1 1
*5
1
*5
BL + tRP
*5
BL + tRP
BL + tRP
BL + tRP 1
WRIT
*1, *2
1
*1, *3
1
*5
tDPL
*5 *1 *1
*1
WRITA
BL-1 + tDAL
*1, *2
1
*1, *3
1
*6
1
*6
1
*6
1
*6
1
*5, *6
BL-1 + tDAL
*6
BL-1 + tDAL
*1
BL-1 + tDAL
*1, *7
BL-1 + tDAL 1
PRE
tRP
*2
1 tRP
1
1
1
1
1 1
1 1
tRP tRP
tRP
*7
PALL
tRP tREFC
tRP tREFC
1
REF
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
*1: Assume all banks are in idle state. *2: Assume output is in High-Z state. *3: tRRD (Min) of other bank (the second command will be asserted) is satisfied. *4: Assume other bank is in active, read or write state. *5: Assume tRAS (Min) is satisfied. *6: Assume other banks are not in READA/WRITA state. *7: Assume the last data have been appeared on DQ. *8: Assume no I/O conflict. Illegal Command.
22
MB81ES171625/173225-12/-15
s MODE REGISTER TABLE
MODE REGISTER SET BA A12 A11 A10 0 or 1
A9
A8*2 0
A7*2 0
A6
A5 CL
A4
A3 BT
A2
A1 BL
A0
ADDRESS MODE REGISTER
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved 1 2 Reserved Reserved Reserved Reserved Reserved
A2 A1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Length BT = 0 1 2 4 8 Reserved Reserved Reserved Full Column BT = 1 *1 Reserved 2 4 8 Reserved Reserved Reserved Reserved
A3 0 1
Burst Type Sequential Interleave
*1: BL = 1 and Full Column are not applicable to the interleave mode. *2: A7 and A8 = 1 are reserved for vender test.
23
MB81ES171625/173225-12/-15
s ABSOLUTE MAXIMUM RATINGS
Parameter Voltage of VCC Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature Symbol VDD, VDDQ VIN, VOUT IOUT TSTG Rating Min -0.5 -0.5 -13 -55 Max +3.0 +3.0 +13 +125 Unit V V mA C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss) Parameter Supply Voltage*1 Input High Voltage* Input Low Voltage*
2
Symbol VDD, VDDQ VSS, VSSQ VIH VIL TA Tj
Value Min 1.65 0 VDDQ-0.4 -0.3 0 0 Typ 1.8 0 Max 1.95 0 VDDQ + 0.3 0.4 +70 +100
Unit V V V V C C
3
Ambient Temperature Junction Temperature*4 *1 : All voltages are referenced to VSS.
*2 : Overshoot limit: VIH (Max) = 3.0 V for pulse width 5 ns acceptable,pulse width measured at 50% of pulse amplitude.
3.0 V
*3 : Undershoot limit: VIL (Min) = VSS -1.5 V for pulse width 5 ns acceptable,pulse width measured at 50% of pulse amplitude.
VIH
Pulse width 5 ns
50% of pulse amplitude
VIH VIH (Min) VIL
VIL (Max) VIL -1.5 V
50% of pulse amplitude
Pulse width 5 ns
*4 : The maximum junction temperature of FCRAM (Tj) should not be more than +100 C. Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI(PD),the thermal resistance of the package(ja),and the maximum ambient temperature of the SiP(TAmax). Tjmax[ C] = TAmax[ C] + ja[ C/W] x Pmax[W] Pmax[W] = PFCRAM + PD WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24
MB81ES171625/173225-12/-15
s CAPACITANCE
(f = 1 MHz, TA = +25 C) Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance Symbol CIN1 CIN2 CI/O Value Min 2.0 2.0 2.0 Typ Max 5.0 5.0 5.0 Unit pF pF pF
25
MB81ES171625/173225-12/-15
s DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Parameter Output High Voltage Output Low Voltage Input Leakage Current (Any Input) Symbol VOH(DC) VOL(DC) ILI Condition IOH = -2 mA IOL = 2 mA 0 V VIN VDDQ; All other pins not under test = 0 V 0 V VIN VDDQ; Data out disabled Burst Length = 1, tRC = Min for BL = 1, tCK = Min, One bank active, Output pin open, Addresses changed up to one time during tCK (Min) , 0 V VIN VIL Max, VIH Min VIN VDDQ CKE = 0 V, All banks idle, tCK = Min, Power down mode, VIL = 0 V, VIH = VDDQ CKE = 0 V, All banks idle, CLK = VDDQ or 0 V, Power down mode, VIL = 0 V, VIH = VDDQ CKE = VDDQ , All banks idle, tCK = Min, NOP command only, Input signals (except to CMD) are changed one time during 30 ns, VIL=0 V, VIH = VDDQ CKE = VDDQ , All banks idle, CLK = VDDQ or 0 V, Input signal are stable, VIL=0 V, VIH = VDDQ Value Min VDDQ -0.2 -5 -5 Max 0.2 5 Unit V V A A
Output Leakage Current
ILO
5
Average Power Supply Current (Operating Current)
IDD1
30
mA
IDD2P Power Supply Current (Precharge Standby Current) IDD2PS
1
mA
1
mA
IDD2N Power Supply Current (Precharge Standby Current)
4
mA
IDD2NS
1
mA
(Continued)
26
MB81ES171625/173225-12/-15
(Continued)
Parameter Symbol Condition CKE = 0 V , Any bank active, tCK = Min, VIL = 0 V, VIH = VDDQ CKE = 0 V , Any bank active, CLK = VDDQ or 0 V, VIL = 0 V, VIH = VDDQ CKE = VDDQ , Any bank active, tCK = Min, NOP command only, Input signals (except to CMD) are changed one time during 30 ns, VIL = 0 V, VIH = VDDQ CKE = VDDQ , Any bank active, CLK = VDDQ or 0 V, Input signals are stable, VIL = 0 V, VIH = VDDQ tCK = Min, Burst Length = 4, Output pin open, All-banks active, Gapless data, 0 V VIN VIL Max, VIH Min VIN VDDQ Auto-refresh; tCK = Min, tREFC = Min, 0 V VIN VIL Max, VIH Min VIN VDDQ Self-refresh; CLK = VDDQ or 0 V, CKE= 0 V, 0 V VIN VIL Max, VIH Min VIN VDDQ Value Min Max Unit
IDD3P
1
mA
IDD3PS
1
mA
MB81ES171625/ Power Supply Current (Active Standby Current) 173225-12 IDD3N MB81ES171625/ 173225-15
13
mA
10
mA
IDD3NS
1
mA
Average Power Supply Current (Burst mode Current)
MB81ES171625/ 173225-12 IDD4 MB81ES171625/ 173225-15
51
mA
40
mA
Average Power Supply Current (Auto Refresh Current)
IDD5
73
mA
Average Power Supply Current (Self Refresh Current)
IDD6
5
mA
Notes: * All voltages are referenced to VSS,VSSQ. * DC characteristics are measured after following "17. Power-Up Initialization" procedure in sFUNCTIONAL DESCRIPTION. * IDD depends on output termination, load conditions, clock rate, number of address and/or command change within certain period. The specified values are obtained with the output open. 27
MB81ES171625/173225-12/-15
s AC CHARACTERISTICS
(1) Basic AC Characteristics (At recommended operating conditions unless otherwise noted.) MB81ES171625/173225 Parameter CL = 1 CL = 2 Symbol Min Clock Period Clock High Time *1 Clock Low Time *1 Input Setup Time * Input Hold Time *
1 1
-12 Max 1000 51.9 21.9 21.9 10.2 10 10 7.8 16 5 Min 30 15 6 6 3 2 0 2.5 2.5 2.5 0.5 23.4 11.7 4.5 4.5 3 2 0 2.5 2.5 2.5 0.5
-15 Max 1000 57 27 27 12 10 10 7.8 16 5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ns
tCK1 tCK2 tCH tCL tSI tHI tRAC tCAC
XRAS Access Time *2 XCAS Access Time *1, *3 Access Time from Clock (tCK = Min) *1, *3, *4 Output in Low-Z *1 Output in High-Z *1, *5 Output Hold Time * *
1, 3
CL = 1 CL = 2 CL = 1 CL = 2
tAC1 tAC2 tLZ tHZ1 tHZ2 tOH tREFI tREF tT
Time between Auto-Refresh command interval *2 Time between Refresh Transition Time
*1: If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) - 0.5] ns should be added to tCAC (Max) , tAC (Max) , tHZ (Max) , and tSI (Min) spec values, [ (tT / 2) - 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values. *2: This value is for reference only. *3: Measured under AC test load circuit shown in " (5) Measurement Condition of AC Characteristics (Load Circuit) ". *4: tAC also specifies the access time at burst mode except for first access at CL = 1. *5: Specified where output buffer is no longer driven. Notes: * AC characteristics are measured after following "17. Power-Up Initialization" procedure in sFUNCTIONAL DESCRIPTION. * AC characteristics assume tT = 1 ns ,10 pF of capacitive and 50 of terminated load. Refer to " (5) Measurement Condition of AC Characteristics (Load Circuit) ". * 0.9 V is the reference level for measuring timing of input/output signals. * Transition times are measured between VIH (Min) and VIL (Max) . Refer to " (6) Set up, Hold and Delay Time".
28
MB81ES171625/173225-12/-15
(2) Base Values for Clock Count/Latency MB81ES171625/173225 Parameter XRAS Cycle Time * XRAS Precharge Time XRAS Active Time XRAS to XCAS Delay Time Write Recovery Time XRAS to XRAS Bank Active Delay Time Data-in to Precharge Lead Time Data-in to Active/ Refresh Command Period Refresh Cycle Time Mode Resister Set Cycle Time Symbol Min tRC tRP tRAS tRCD tWR tRRD tDPL tDAL tREFC tRSC 75 30 45 30 11.7 11.7 11.7 1cyc+ tRP 75 45
RC)
-12 Max 110000 Min 75 30 45 30 15 15 15
-15 Max 110000
Unit ns ns ns ns ns ns ns ns ns ns
1cyc+ tRP 75 45
*: tRC (Min) is not sum of tRAS (Min) and tRP (Min) . Actual clock count of tRC ( and tRP (Min) . (3) Clock Count Formula Clock Base Value Clock Period (Round up to a whole number)
must satisfy tRC (Min) , tRAS (Min)
Note: All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round up to a whole number) .
29
MB81ES171625/173225-12/-15
(4) Latency - Fixed Values (The latency values on these parameters are fixed regardless of clock period.) MB81ES171625/173225 Parameter Symbol Unit -12 -15 CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay XCAS to XCAS Delay (Min) XCAS Bank Delay (Min) CL = 1 CL = 2 CL = 1 CL = 2 CL = 1 CL = 2
CKE DQZ1 DQZ2 DQD OWD DWD ROH1 ROH2 BSH1 BSH2 CCD CBD
1 1 2 0 2 0 1 2 1 2 1 1
1 1 2 0 2 0 1 2 1 2 1 1
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
(5) Measurement Condition of AC Characteristics (Load Circuit)
R1 = 50
Output
0.9 V
CL = 10 pF
30
MB81ES171625/173225-12/-15
(6) Setup, Hold and Delay Time
tCK
tCH 1.4 V
tCL
CLK
0.4 V
0.9 V
tSI
tHI 1.4 V
Input (Control, Addr. & Data)
VALID
0.9 V 0.4 V tHZ tOH
tCAC, tAC tLZ VOH
Output
VOL
0.9 V
VALID
Notes : * Reference level of input/output signal is 0.9 V. * Access time is measured at 0.9 V. * AC characteristics are also measured in this condition.
: INVALID
(7) Delay Time for Power Down Exit
CLK
H or L
tSI
1 clock (Min)
CKE
Command
H or L
NOP
ACTV
31
MB81ES171625/173225-12/-15
(8) Pulse Width
CLK
tRC, tRP, tRAS, tRCD, tWR, tREFI,
Input (Control)
tREFC, tDPL, tDAL, tRSC, tRRD
COMMAND COMMAND
: INVALID Notes : * These parameters are a limit value of the rising edge of the clock from one command input to the next input. * Measurement reference voltage is 0.9 V.
(9) Access Time
CLK
tRAC
XRAS
tRCD tCAC
XCAS
tAC 1 clock at CL = 2 tAC tAC
DQ (Output)
Q (Valid)
Q (Valid)
Q (Valid)
32
MB81ES171625/173225-12/-15
s TIMING DIAGRAMS
1. Clock Enable - READ and WRITE Suspend (@ BL = 4)
CLK
tSI tHI tSI tHI tSI tHI
CKE
(1 clock)*1
CKE
1
(1 clock)*1
CKE
1 2
CLK (Internal)
2
DQ (Read)
Q1
Q2
(NO Change)
2
Q3
(NO Change)
2
Q4
DQ (Write)
D1
NOT 3 Written
D2
NOT 3 Written
D3
D4
*1: The latency of the CKE (
CKE)
is one clock.
*2: During the read mode, burst counter will not be increased/decreased at the next clock of the CSUS command. Output data remains the same data. *3: During the write mode, data at the next clock of the CSUS command is ignored.
2. Clock Enable - Power Down Entry and Exit
CLK
tSI (Min) 1 clock (Min)
CKE
Command
1 NOP
PD (NOP)
H or L
NOP
2
ACTV
3
tREF (Max)
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2: The NOP command should be asserted in conjunction with CKE. *3: The ACTV command can be latched after tSI + 1 clock (Min) .
33
MB81ES171625/173225-12/-15
3. Column Address to Column Address Input Delay
CLK
XRAS
tRCD (Min)
CCD CCD CCD CCD
XCAS
Address
Row Address
Column Address
Column Address
Column Address
Column Address
Column Address
Note : XCAS to XCAS delay (
CCD)
can be one or more clock period.
4. Different Bank Address Input Delay
CLK
tRRD (Min)
XRAS
tRCD (Min)
CBD CBD
XCAS
tRCD (Min)
Address
Row Address
Row Address
Column Address
Column Address
Column Address
Column Address
BA
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : XCAS Bank delay (
CBD)
can be one or more clock period.
34
MB81ES171625/173225-12/-15
5. DQM - Input Mask and Output Disable (@ CL = 2, BL = 4)
CLK
DQM (@ Read)
DQZ2(2clocks)
DQ (@ Read)
Q1
Q2
High-Z
Q4
End of burst
DQM (@ Write)
DQD
(same clock)
DQ (@ Write)
D1
Masked
D3
D4
End of burst
6. Precharge Timing (Applied to the Same Bank)
CLK
tRAS (Min)
Command
ACTV
PRE
Note : PRE means `PRE' or `PALL'.
35
MB81ES171625/173225-12/-15
7. READ Interrupted by Precharge (Example @ CL = 2, BL = 4)
CLK
Command
PRE
ROH2 (2 clocks)
High-Z DQ
Q1
Command
PRE
ROH2 (2 clocks)
DQ
High-Z
Q1 Q2
Command
PRE
ROH2 (2 clocks)
High-Z DQ
Q1 Q2 Q3
Command
PRE No effect (end of burst)
DQ
Q1
Q2
Q3
Q4
Notes : * In case of CL = 1, the ROH1 is 1 clock. * In case of CL = 2, the ROH2 is 2 clocks. * PRE means `PRE' or `PALL'.
36
MB81ES171625/173225-12/-15
8. READ Interrupted by Burst Stop (Example @ BL = Full Column)
CLK
Command (CL = 1)
BST
BSH1(1 clock)
DQ
Qn - 2
Qn - 1
Qn
High-Z
Command (CL = 2)
BST
BSH2(2 clocks)
High-Z DQ
Qn - 2 Qn - 1 Qn Qn + 1
9. WRITE Interrupted by Burst Stop (Example @ BL = 2)
CLK
Command
BST
Command
DQ
LAST Dn
Masked by BST
37
MB81ES171625/173225-12/-15
10. WRITE Interrupted by Precharge
CLK
Command
tDPL (Min)
PRE
ACTV tRP (Min)
DQ
Dn-1
LAST Dn
Masked by Precharge
Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied. PRE means `PRE' or `PALL'.
11. READ Interrupted by WRITE (Example @ CL = 2, BL = 4)
CLK
OWD
Command
READ
WRIT
DQM
1
2
DQZ2(2 clocks)
3
DWD
DQ
Q1
D1
D2
*1: The First DQM makes high-impedance state High-Z between the last output and the first input data. *2: The Second DQM makes internal output data mask to avoid bus contention. *3: The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
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MB81ES171625/173225-12/-15
12. WRITE to READ Timing (Example @ CL = 1, BL = 4)
CLK
tWR (Min) WRIT READ
Command
DQM
tCAC (Max)
tAC
tAC
tAC
DQ
D1
D2
D3 Masked by READ
Q1
Q2
Q3
Notes : * The Read command should be issued after tWR of the final data input is satisfied. * The write data after the READ command is masked by the READ command.
13. READ with Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)
CLK
Command
ACTV
READA
NOP or DESL
ACTV
BL + tRP
*
DQM
DQ
Q1
Q2
*: The Next ACTV command should be issued after BL + tRP from the READA command.
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MB81ES171625/173225-12/-15
14. WRITE With Auto-Precharge (Example @ CL = 2, BL = 2 Applied to same bank)
CLK
tDAL (Min) (BL - 1) + tDAL*
Command
ACTV
WRITA
NOP or DESL
ACTV
DQM
DQ
D1
D2
*: The Next command should be issued after (BL - 1) + tDAL from the WRITA command. Notes: * If the final data is masked by DQM, the precharge does not start at the clock of the final data input. * Once the auto precharge command is asserted, no new command within the same bank can be issued. * The Auto-precharge command can not be invoked at full column burst operation.
15. Auto-Refresh Timing
CLK
Command
REF1
NOP2
NOP2 tREFC (Min)
NOP2
REF
NOP2 tREFC (Min)
Command*3
BA
H or L *4
H or L *4
BA
*1: All banks should be precharged prior to the first Auto-refresh command (REF) . *2: Either the NOP or DESL command should be asserted within tREFC period while Auto-refresh mode. *3: Any activation command such as the ACTV or MRS commands other than the REF command should be asserted after tREFC from the last REF command. *4: Bank select is ignored at REF command. The refresh address and bank select are selected by the internal refresh counter.
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MB81ES171625/173225-12/-15
16. Self-Refresh Entry and Exit Timing
Entry
CLK
tSI tSI (Min)
Exit
4
CKE
tREFC
Command
NOP 1
SELF
H or L
SELFX 2
NOP 3
Command
*1: The Precharge command (PRE or PALL) should be asserted if any bank is active prior to the Self-refresh Entry command (SELF) . *2: The Self-refresh Exit command (SELFX) is latched after tSI. *3: Either the NOP or DESL command can be used during tREFC period. *4: CKE should be held high for at least one tREFC period after tSI.
17. Mode Register Set Timing
CLK
tRSC (Min)
Command
MRS
NOP or DESL
ACTV
Address
MODE
Row Address
Note : The Mode Register Set command (MRS) should be asserted only after all banks have been precharged and DQ is in High-Z.
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MB81ES171625/173225-12/-15
s ORDERING INFORMATION
Part number MB81ES171625-12WFKT MB81ES171625-15WFKT MB81ES173225-12WFKT MB81ES173225-15WFKT Configuration 512 K word x 16 bit x 2 bank 512 K word x 16 bit x 2 bank 256 K word x 32 bit x 2 bank 256 K word x 32 bit x 2 bank Shipping form Wafer Wafer Wafer Wafer Remarks
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MB81ES171625/173225-12/-15
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0306 (c) FUJITSU LIMITED Printed in Japan

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